Semiconductor device having the effect that the drop in the current gain is kept to the minimum, when the substrate density is amplified and that the variation in the collector current is improved

ABSTRACT

A semiconductor device includes a SiGe base bipolar transistor. The SiGe base bipolar transistor includes an emitter layer, a collector layer and a SiGe base layer formed of silicon containing germanium. A Ge concentration of the SiGe base layer is increased from 0% to 10% from a side of the emitter layer towards a side of the collector layer.

CROSS-REFERENCE TO RELATED PATENT APPLICATIONS

[0001] This application is a division of application Ser. No.09/864,330, filed May 25, 2001, now pending, and based on JapanesePatent Application No. 2000-158711, filed May 29, 2000, by TakasukeHashimoto. This application claims only subject matter disclosed in theparent application and therefore presents no new matter.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor device and asemiconductor manufacturing method. More particularly, the presentinvention relates to a semiconductor device and a semiconductormanufacturing method, which can minimize a drop in a current gain at atime of an increase in a collector current density and also improve avariation in a collector current.

[0004] 2. Description of the Related Art

[0005] As a conventional technique, for example, there is a techniquedisclosed in Japanese Laid Open Patent Application (JP-A-Heisei,7-147287). That is, this is a SiGe base bipolar transistor, in whicheach of a base layer and a collector layer are constituted by a singlecrystal silicon layer containing germanium (Element Symbol: Ge), and anoccurrence of a parasitic energy barrier is protected in abase-collector junction region, and a drop in a cut-off frequency issuppressed.

[0006]FIG. 1 is a device section view describing a conventional SiGebase bipolar transistor. In FIG. 1, a symbol 201 denotes a P-typesilicon substrate. A symbol 202 denotes an N⁺-type buried layer. Asymbol 203A denotes a first collector layer. A symbol 203B denotes asecond collector layer. A symbol 205 denotes an insulation separationoxide film. A symbol 206 denotes a diffusion layer to pull out acollector. A symbol 207 denotes an oxide film. A symbol 208 denotes aP-type poly-crystal silicon layer to pull out an outer base. A symbol209 denotes a silicon nitride film. A symbol 210 denotes a P-type SiGebase layer (silicon germanium base layer). A symbol 211 denotes asilicon nitride film. A symbol 212 denotes a poly-crystal silicon filmto pull out an emitter. And, a symbol 213 denotes an emitter layer.

[0007] In the conventional SiGe base bipolar transistor, the N⁺-typeburied layer 202 having a high concentration and the first collectorlayer 203A having a first Ge concentration distribution and the secondcollector layer 203B having a second Ge concentration distribution areformed on the P-type silicon substrate 201, as shown in FIG. 1. TheP-type SiGe base layer 210 resulting from a selectively epitaxial growthand the emitter layer 213 constituted by an N-type diffusion layer areformed on the first collector layer 203A.

[0008]FIG. 2 is a graph showing the profile of a Ge percentage content(germanium percent content) and an impurity concentration with respectto a depth of the conventional SiGe base bipolar transistor. In theconventional SiGe base bipolar transistor, the first collector layer203A having the first Ge concentration distribution and the secondcollector layer 203B having the second Ge concentration distribution(germanium concentration distribution) are formed in the N⁺-type buriedlayer 202 having the high concentration in which N-type impurity isdoped at about 10²⁰ cm⁻³, as shown in FIG. 2. Then, the P-type SiGe baselayer 210 in which P-type impurity is doped at about 5×10¹⁸ cm⁻³ and thepoly-crystal silicon film 212 to pull out an emitter in which the N-typeimpurity is doped at about 2×10²⁰ cm⁻³ are formed on the first collectorlayer 203A. The emitter layer 213 is formed by using the impuritythermal diffusion from the poly-crystal silicon film 212 to pull out anemitter in which the N-type impurity is doped.

[0009] With regard to the Ge concentration distribution of the P-typeSiGe base layer 210, in the P-type SiGe base layer 210, an emitterregion side has a low distribution, and a collector region side has ahigh distribution. That is, the emitter region side has a Ge percentagecontent of 0%, and the collector region side has a slant concentrationdistribution having a percentage content of 10%. FIG. 3 shows an energyband structure at this time.

[0010]FIG. 3 is a graph showing an energy band at the slant Ge profile(slant germanium profile). As shown in FIG. 3, in the case of theconventional SiGe base bipolar transistor, in the P-type crystal SiGebase layer 210, an inclination can be set for a conductive band side ofan energy band, correspondingly to a Ge composition ratio (germaniumcomposition ratio). Thus, an electron implanted from an emitter isaccelerated in the P-type SiGe base layer 210 by an electrical fieldcaused by the slant energy band structure. Hence, it is possible toreduce a base transit time of the electron and accordingly improve acut-off frequency fT.

[0011] However, in the case of the conventional SiGe base bipolartransistor, in order to make the cut-off frequency fT higher by usingthe slant Ge profile, it is necessary to reduce a thickness of theP-type SiGe base layer 210. For example, it is noted that the thicknessof the P-type SiGe base layer 210 is about 90 nm and the cut-offfrequency fT=20 GHz. In order to set the cut-off frequency fT to 60 GHz,the thickness of the P-type SiGe base layer 210 must be reduced to about30 nm. This brings about the following problems.

[0012] As the first problem, a constant region is narrow because of adrop in a current gain hFE in a high current region when the slant Geprofile is used, although an analog circuit especially requires that acurrent gain hFE (=collector current/base current) is constant in a widecurrent region of a collector current.

[0013] The reason is as follows. In the profile that the impurityconcentration in the base is constant and the Ge concentration is slantsuch as the slant Ge profile, a collector current density Jc isrepresented by the following equation (1): $\begin{matrix}{{J\quad c} = {\frac{q\quad D\quad n\quad n\quad i^{2}}{N\quad A\quad W\quad b}\frac{\Delta \quad E\quad g\quad G\quad {e\left( {g\quad r\quad a\quad d\quad e} \right)}}{k\quad T}{\exp \left\lbrack \frac{\Delta \quad E\quad g\quad G\quad {e(0)}}{k\quad T} \right\rbrack}}} & {{equation}\quad (1)}\end{matrix}$

[0014]^(Δ)EgGe(0): Contraction Amount of Band Gap by Ge at Tip ofDepletion Layer between Emitter And Base

[0015]^(Δ)EgGe(grade): Ge Slant Amount in Neutral Base

[0016] Dn: Diffusion Constant of Electron in Base

[0017] NA: Base Impurity Concentration

[0018] Wb: Base Width

[0019] ni: Intrinsic Carrier Density

[0020] q: Charge

[0021] In the case of the slant Ge profile of the conventional SiGe basebipolar transistor, when the thickness of the P-type SiGe base layer 210is reduced, this reduction causes the Ge inclinations (germaniuminclinations) to be sharp at the positions of the formations of theemitter-base junction and the depletion layer between the emitter andthe base. This results in a large reduction in a contraction amount^(Δ)E_(g,Ge)(0) of a band gap when the depletion layer between theemitter and the base is contracted as a voltage between the emitter andthe base is made higher. Thus, the collector current is dropped inaccordance with the equation (1), and the current gain hFE is largelydropped.

[0022] The second problem is the occurrence of a large variation in acollector current flowing when a certain voltage is applied between thebase and the emitter. The variation in the collector current has greatinfluence on a circuit operation when a transistor is used as a constantcurrent source, for example, such as a case of an ECL circuit.

[0023] The reason of the variation in this collector current is asfollows. The emitter layer 213 is formed by using the impurity thermaldiffusion from the poly-crystal silicon film 212 to pull out an emitterin which the N-type impurity is doped. The reduction in the thickness ofthe P-type SiGe base layer 210 causes the Ge inclination (germaniuminclination) to be sharp at the position where the emitter-base junctionis formed. As a result, the slight variation at the junction positionleads to the difference of the contraction amount ^(Δ)E_(g,Ge)(0) in theband gap. That is, the collector current is proportional to thecontraction amount ^(Δ)E_(g,Ge)(0) in the band gap as an exponentialfunction, which brings about the large variation in the collectorcurrent.

[0024] Japanese Laid Open Patent Application (JP-A-2000-31162) disclosesthe following hetero junction bipolar transistor. The hetero junctionbipolar transistor is provided with: a collector layer constituted by asemiconductor containing a first conductive type impurity; a base layerthat is provided adjacently to the collector layer and constituted by acompound crystal semiconductor containing a second conductive typeimpurity; and an emitter layer that is provided opposite to thecollector layer with the base layer between and constituted by thesemiconductor containing the first conductive type impurity. The baselayer is provided such that a band gap of the compound semiconductor isgradually reduced from the emitter side towards the collector side and aconcentration of the second conductive type impurity is graduallyreduced from the emitter side towards the collector side.

[0025] Japanese Laid Open Patent Application (JP-A-Heisei, 11-214399)discloses the following bipolar semiconductor device. The bipolarsemiconductor device is provided with: a semiconductor layer having afirst conductive type of a buried layer so as to form a collectorregion, on a substrate; a first insulation film formed on thesemiconductor layer; a second conductive type of a first conductive filmsimilarly formed on the semiconductor layer so as to form a base region,a second conductive type of a second conductive film which is formed onthe first insulation film and connected to the first conductive film soas to form a base pull-out electrode; and a first conductive type of athird conductive film which is separated through a second insulationfilm from the second conductive film and formed on the first conductivefilm so as to form an emitter region, wherein the first insulation filmand the second conductive film are coated with glass material insulationfilm, and the surface of the glass material insulation film is flat.

[0026] Japanese Laid Open Patent Application (JP-A-Heisei, 10-79394)discloses the following bipolar transistor. The bipolar transistor atleast contains: a first conductive type of a single crystal siliconlayer; a many-layer film composed of a first insulation film having anopening provided on a surface of the first conductive type of the singlecrystal silicon layer, a second conductive type of a poly-crystal layerof a conductive type opposite to the first conductive type, and a secondinsulation film; a first conductive type of a single crystal silicongermanium layer provided in the opening; a second conductive type of asingle crystal silicon germanium layer provided on the first conductivetype of the single crystal silicon germanium layer; and a secondconductive type of a poly-crystal silicon germanium layer placed incontact with both the second conductive type of the single crystalsilicon germanium layer and the second conductive type of thepoly-crystal layer.

[0027] Moreover, Japanese Publication Patent Application (JP-B2-Heisei,07-44185) discloses the following semiconductor device. Thesemiconductor device is a bipolar transistor, in which on a siliconsubstrate or a silicon epitaxial layer having a first conductive type,has a compound crystal layer composed of silicon and germanium, and hasa second conductive type impurity layer in the compound crystal, and hasa silicon layer having a first conductive type impurity on the compoundcrystal layer of the silicon and the germanium, and has a heterojunction in a manner of forming a p-n junction on a boundary between thecompound crystal layer of the silicon and the germanium and the siliconlayer, wherein it is formed on the silicon substrate or the siliconepitaxial layer so that a germanium concentration included in thecompound crystal composed of the silicon and the germanium is graduallyhigher towards the boundary between an outer compound crystal layer andthe silicon layer thereon.

SUMMARY OF THE INVENTION

[0028] The present invention is accomplished in view of the abovementioned problems. Therefore, an object of the present invention is toprovide a semiconductor device and a semiconductor manufacturing method,which can minimize a drop in a current gain at a time of an increase ina collector current density and also improve a variation in a collectorcurrent.

[0029] In order to achieve an aspect of the present invention, asemiconductor device, includes: a SiGe base bipolar transistor; andwherein the SiGe base bipolar transistor includes: an emitter layer; acollector layer; and a SiGe base layer formed of silicon containinggermanium, and wherein a Ge concentration of the SiGe base layer isincreased from 0% to 10% from a side of the emitter layer towards a sideof the collector layer.

[0030] In this case, the SiGe base bipolar transistor includes: a P-typesilicon substrate; and an N⁺-type buried layer having a highconcentration formed in the P-type silicon substrate, and wherein thecollector layer is formed of an N-type having a low concentration and isformed on the N⁺-type buried layer, and wherein the SiGe base bipolartransistor further including: an undoped SiGe layer in which an impurityis not doped, the undoped SiGe layer being formed on the N-typecollector layer; a first SiGe base layer as a part of the SiGe baselayer having a first Ge concentration distribution formed on the undopedSiGe layer; and a second SiGe base layer as another part of the SiGebase layer having a second Ge concentration distribution formed on thefirst SiGe base layer, and wherein the emitter layer is formed of anN-type diffusion layer formed in the second SiGe base layer.

[0031] In this case, an N-type impurity is doped at about 10¹⁶ cm⁻³ asthe low concentration of the N-type collector layer, and the N-typeimpurity is doped at about 10²⁰ cm⁻³ as the high concentration of theN⁺-type buried layer.

[0032] Also in this case, the undoped SiGe layer has a Ge concentrationof about 10% and a thickness of about 30 nm.

[0033] Further in this case, a P-type impurity is doped at about 1×10¹⁹cm⁻³ in the first SiGe base layer and the second SiGe base layer.

[0034] Further in this case, the semiconductor device further includes:a poly-crystal silicon film to pull out an emitter in which an N-typeimpurity is doped at about 2×10²⁰ cm⁻³, the poly-crystal silicon filmbeing formed on the second SiGe base layer.

[0035] In this case, the emitter layer is formed as a result that animpurity thermal diffusion is performed on the poly-crystal siliconfilm.

[0036] Also in this case, the SiGe base layer includes a first SiGe baselayer and a second SiGe base layer, and wherein a thickness of thesecond SiGe base layer is about 20 nm, and a Ge concentration in thesecond SiGe base layer is increased from about 0% to about 2% from theside of the emitter layer towards the side of the collector layer, andwherein a thickness of the first SiGe base layer is about 10 nm, and aGe concentration in the first SiGe base layer is increased from about 2%to about 10% from the side of the emitter layer towards the side of thecollector layer.

[0037] Further in this case, the SiGe base bipolar transistor including:a P-type silicon substrate; and an N⁺-type buried layer having a highconcentration in which an N-type impurity is doped at about 10²⁰ cm⁻³formed in the P-type silicon substrate, and wherein the collector layeris formed of an N-type having a low concentration in which the N-typeimpurity is doped at about 10¹⁶ cm⁻³ and is formed on the N⁺-type buriedlayer, and wherein the SiGe base bipolar transistor further including:an undoped SiGe layer in which an impurity is not doped, wherein theundoped SiGe layer is formed on the N-type collector layer and has a Geconcentration of about 10% and a thickness of about 30 nm; a third SiGebase layer as a part of the SiGe base layer having a third Geconcentration distribution formed on the undoped SiGe layer; a fourthSiGe base layer as another part of the SiGe base layer having a fourthGe concentration distribution formed on the third SiGe base layer; and aSi base layer as other part of the SiGe base layer.

[0038] In this case, a P-type impurity is doped at about 1×10¹⁹ cm⁻³ inthe third SiGe base layer, the fourth SiGe base layer and the Si baselayer.

[0039] Also in this case, the semiconductor device further includes: apoly-crystal silicon film to pull out an emitter in which an N-typeimpurity is doped at about 2×10²⁰ cm⁻³, the poly-crystal silicon filmbeing formed on the Si base layer.

[0040] Further in this case, the emitter layer is formed as a resultthat an impurity thermal diffusion is performed on the poly-crystalsilicon film.

[0041] In this case, the SiGe base layer includes a third SiGe baselayer and a fourth SiGe base layer, and a Si base layer, and wherein athickness of the Si base layer is about 20 nm, and wherein a thicknessof the fourth SiGe base layer is about 5 nm, and a Ge concentration inthe fourth SiGe base layer is increased from about 0% to about 2% fromthe side of the emitter layer towards the side of the collector layer,and wherein a thickness of the third SiGe base layer is about 5 nm, anda Ge concentration in the third SiGe base layer is increased from about2% to about 10% from the side of the emitter layer towards the side ofthe collector layer.

[0042] In order to achieve another aspect of the present invention, asemiconductor with a SiGe base bipolar transistor manufacturing method,includes: (a) providing an emitter layer; (b) providing a collectorlayer; and (c) providing a SiGe base layer formed of silicon containinggermanium, and wherein a Ge concentration of the SiGe base layer isincreased from 0% to 10% from a side of the emitter layer towards a sideof the collector layer.

[0043] Also in this case, the semiconductor with a SiGe base bipolartransistor manufacturing method further includes: (d) providing a P-typesilicon substrate; and (e) forming an N⁺-type buried layer having a highconcentration in the P-type silicon substrate, and wherein the collectorlayer is formed of an N-type having a low concentration and is formed onthe N⁺-type buried layer, and wherein the semiconductor with the SiGebase bipolar transistor manufacturing method further including: (f)forming an undoped SiGe layer in which an impurity is not doped on theN-type collector layer; (g) forming a first SiGe base layer as a part ofthe SiGe base layer having a first Ge concentration distribution on theundoped SiGe layer; and (h) forming a second SiGe base layer as anotherpart of the SiGe base layer having a second Ge concentrationdistribution on the first SiGe base layer, and wherein the emitter layeris formed of an N-type diffusion layer formed in the second SiGe baselayer.

[0044] In this case, an N-type impurity is doped at about 10¹⁶ cm⁻³ asthe low concentration of the N-type collector layer, and the N-typeimpurity is doped at about 10²⁰ cm⁻³ as the high concentration of theN⁺-type buried layer.

[0045] Also in this case, the undoped SiGe layer has a Ge concentrationof about 10% and a thickness of about 30 nm.

[0046] Further in this case, a P-type impurity is doped at about 1×10¹⁹cm⁻³ in the first SiGe base layer and the second SiGe base layer.

[0047] In this case, the semiconductor with a SiGe base bipolartransistor manufacturing method further includes: (i) forming apoly-crystal silicon film to pull out an emitter in which an N-typeimpurity is doped at about 2×10²⁰ cm⁻³ on the second SiGe base layer.

[0048] Also in this case, the emitter layer is formed as a result thatan impurity thermal diffusion is performed on the poly-crystal siliconfilm.

[0049] Further in this case, the SiGe base layer includes a first SiGebase layer and a second SiGe base layer, and wherein a thickness of thesecond SiGe base layer is about 20 nm, and a Ge concentration in thesecond SiGe base layer is increased from about 0% to about 2% from theside of the emitter layer towards the side of the collector layer, andwherein a thickness of the first SiGe base layer is about 10 nm, and aGe concentration in the first SiGe base layer is increased from about 2%to about 10% from the side of the emitter layer towards the side of thecollector layer.

[0050] In this case, the semiconductor with a SiGe base bipolartransistor manufacturing method further includes: (j) providing a P-typesilicon substrate; and (k) forming an N⁺-type buried layer having a highconcentration in which an N-type impurity is doped at about 10²⁰ cm⁻³ inthe P-type silicon substrate, and wherein the collector layer is formedof an N-type having a low concentration in which the N-type impurity isdoped at about 10¹⁶ cm⁻³ and is formed on the N⁺-type buried layer, andwherein the semiconductor with the SiGe base bipolar transistormanufacturing method further including: (I) forming an undoped SiGelayer in which an impurity is not doped on the N-type collector layer,the undoped SiGe layer having a Ge concentration of about 10% and athickness of about 30 nm; (m) forming a third SiGe base layer as a partof the SiGe base layer having a third Ge concentration distribution onthe undoped SiGe layer; (n) forming a fourth SiGe base layer as anotherpart of the SiGe base layer having a fourth Ge concentrationdistribution on the third SiGe base layer; and (o) forming a Si baselayer as other part of the SiGe base layer.

[0051] Also in this case, a P-type impurity is doped at about 1×10¹⁹cm⁻³ in the third SiGe base layer, the fourth SiGe base layer and the Sibase layer.

[0052] Further in this case, the semiconductor with a SiGe base bipolartransistor manufacturing method, further includes: (p) forming apoly-crystal silicon film to pull out an emitter in which an N-typeimpurity is doped at about 2×10²⁰ cm⁻³ on the Si base layer.

[0053] In this case, the emitter layer is formed as a result that animpurity thermal diffusion is performed on the poly-crystal siliconfilm.

[0054] Also in this case, the SiGe base layer includes a third SiGe baselayer and a fourth SiGe base layer, and a Si base layer, and wherein athickness of the Si base layer is about 20 nm, and wherein a thicknessof the fourth SiGe base layer is about 5 nm, and a Ge concentration inthe fourth SiGe base layer is increased from about 0% to about 2% fromthe side of the emitter layer towards the side of the collector layer,and wherein a thickness of the third SiGe base layer is about 5 nm, anda Ge concentration in the third SiGe base layer is increased from about2% to about 10% from the side of the emitter layer towards the side ofthe collector layer.

[0055] The purpose of the present invention characteristically lies in asemiconductor device containing a SiGe base bipolar transistor having aslant Ge profile in which a Ge concentration of a SiGe base layer isincreased from 0% to 10% from an emitter region side towards a collectorregion side.

[0056] In this case, an N⁺-type buried layer having a high concentrationand an N-type collector layer having a low concentration are formed on aP-type silicon substrate of the SiGe base bipolar transistor, and anundoped SiGe layer in which an impurity is not doped, a first SiGe baselayer having a first Ge concentration distribution and a second SiGebase layer having a second Ge concentration distribution are formed onthe N-type collector layer having the low concentration, and an emitterlayer made of an N-type diffusion layer is formed on the second SiGebase layer.

[0057] Also in this case, the SiGe base bipolar transistor is formedsuch that the N-type collector layer having the low concentration inwhich an N-type impurity is doped at about 10¹⁶ cm⁻³ is formed on theN⁺-type buried layer having the high concentration in which the N-typeimpurity is doped at about 10²⁰ cm⁻³.

[0058] Further in this case, the SiGe base bipolar transistor is formedsuch that the undoped SiGe layer having a Ge concentration of about 10%and a thickness of about 30 nm, the first SiGe base layer having a firstGe concentration distribution and the second SiGe base layer having asecond Ge concentration distribution are formed on the N-type collectorlayer having the low concentration.

[0059] In this case, the SiGe base bipolar transistor is formed suchthat the P-type impurity is doped at about 1×10¹⁹ cm⁻³in the first SiGebase layer and the second SiGe base layer.

[0060] Also in this case, the SiGe base bipolar transistor is formedsuch that a poly-crystal silicon film to pull out an emitter in whichthe N-type impurity is doped at about 2×10²⁰ cm⁻³ is formed on thesecond SiGe base layer.

[0061] Further in this case, the emitter layer of the SiGe base bipolartransistor is formed by using the impurity thermal diffusion from thepoly-crystal silicon film to pull out the emitter in which the N-typeimpurity is doped.

[0062] In this case, the SiGe base bipolar transistor is designed suchthat a thickness of the second SiGe base layer is about 20 nm, a Geconcentration is increased from about 0% to about 2% from the emitterregion side towards the collector region side in the second SiGe baselayer, a thickness of the first SiGe base layer is about 10 nm, and a Geconcentration in the first SiGe base layer is increased from about 2% toabout 10%.

[0063] Also in this case, the SiGe base bipolar transistor is formedsuch that the N-type collector layer of the low concentration in whichthe N-type impurity is doped at about 10¹⁶ cm⁻³ on the N⁺-type buriedlayer having the high concentration in which the N-type impurity isdoped at about 10²⁰ cm⁻³, and the undoped SiGe layer having a Geconcentration of about 10% and a thickness of about 30 nm, a third SiGebase layer having a third Ge concentration distribution, a fourth SiGebase layer having a fourth Ge concentration distribution, and a Si baselayer are formed on the N-type collector layer having the lowconcentration.

[0064] Further in this case, the SiGe base bipolar transistor is formedby the formation of a poly-crystal silicon film to pull out an emitter,in which the P-type impurity is doped at about 1×10¹⁹ cm⁻³ on the thirdSiGe base layer, the fourth SiGe base layer and the Si base layer, andthe N-type impurity is doped at about 2×10²⁰ cm⁻³ on the Si base layer.

[0065] In this case, the emitter layer of the SiGe base bipolartransistor is formed by using the impurity thermal diffusion from thepoly-crystal silicon film to pull out the emitter in which the N-typeimpurity is doped.

[0066] Also in this case, the SiGe base bipolar transistor is designedsuch that a thickness of the Si base layer is about 20 nm, a thicknessof the fourth SiGe base layer is about 5 nm, a Ge concentration isincreased from about 0% to about 2% from the emitter region side in thefourth SiGe base layer, a thickness of the third SiGe base layer isabout 5 nm, and a Ge concentration in the third SiGe base layer isincreased from about 2% to about 10%.

[0067] The semiconductor manufacturing method has a step of forming aSiGe base bipolar transistor having a slant Ge profile in which a Geconcentration of a SiGe base layer is increased from 0% to 10% from anemitter region side towards a collector region side.

[0068] In this case, the present invention further includes the stepsof: forming the N-type collector layer having the low concentration inwhich the N-type impurity is doped at about 10¹⁶ cm⁻³, on the N⁺-typeburied layer having the high concentration in which the N-type impurityis doped at about 10²⁰ cm⁻³; forming the undoped SiGe layer having a Geconcentration of about 10% and a thickness of about 30 nm, the firstSiGe base layer having a first Ge concentration distribution, and thesecond SiGe base layer having a second Ge concentration distribution, onthe N-type collector layer having the low concentration; doping theP-type impurity at about 1×10¹⁹ cm⁻³ on the first SiGe base layer andthe second SiGe base layer; forming a poly-crystal silicon film to pullout an emitter in which the N-type impurity is doped at 2×10²⁰ cm⁻³, onthe second SiGe base layer; and setting a thickness of the second SiGebase layer to about 20 nm, increasing the Ge concentration from about 0%to about 2% from an emitter region side towards a collector region sidein the second SiGe base layer, setting a thickness of the first SiGebase layer to about 10 nm, and increasing the Ge concentration in thefirst SiGe base layer from about 2% to about 10%.

[0069] The semiconductor manufacturing method further includes the stepsof: forming the N-type collector layer having the low concentration inwhich the N-type impurity is doped at about 10¹⁶ cm⁻³, on the N⁺-typeburied layer having the high concentration in which the N-type impurityis doped at about 10²⁰ cm⁻³; forming the undoped SiGe layer having a Geconcentration of about 10% and a thickness of about 30 nm, a third SiGebase layer having a third Ge concentration distribution, a fourth SiGebase layer having a fourth Ge concentration distribution and a Si baselayer, on the N-type collector layer having the low concentration;doping the P-type impurity at about 1×10¹⁹ cm⁻³ on the third SiGe baselayer, the fourth SiGe base layer and the Si base layer; forming apoly-crystal silicon film to pull out an emitter in which the N-typeimpurity is doped at 2×10²⁰ cm⁻³, on the Si base layer; forming anemitter layer by using the impurity thermal diffusion from thepoly-crystal silicon film to pull out the emitter in which the N-typeimpurity is doped; and setting a thickness of the Si base layer to about20 nm, setting a thickness of the fourth SiGe base layer to about 5 nm,increasing the Ge concentration from about 0% to about 2% from anemitter region side in the fourth SiGe base layer, and also setting athickness of the third SiGe base layer to about 5 nm, and thenincreasing the Ge concentration in the third SiGe base layer from about2% to about 10%.

BRIEF DESCRIPTION OF THE DRAWINGS

[0070]FIG. 1 is a device section view describing a conventional SiGebase bipolar transistor;

[0071]FIG. 2 is a graph showing a slant Ge profile and an impurityconcentration with respect to a depth of the conventional SiGe basebipolar transistor;

[0072]FIG. 3 is a graph showing an energy band at a slant Ge profile;

[0073]FIG. 4 is a device section view describing a semiconductor deviceaccording to a first embodiment of the present invention;

[0074]FIG. 5 is a graph showing a slant Ge profile and an impurityconcentration with respect to a depth of the semiconductor deviceaccording to the first embodiment;

[0075]FIG. 6 is a graph describing a change in a current gain withrespect to a collector current density; and

[0076]FIG. 7 is a graph showing a slant Ge profile and an impurityconcentration with respect to a depth of a semiconductor deviceaccording to a second embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0077] An embodiment of an appearance inspection method according to thepresent invention will be described below with reference to the attacheddrawings.

[0078]FIG. 4 is a device section view describing a SiGe base bipolartransistor (semiconductor device) according to a first embodiment of thepresent invention. In FIG. 4, a symbol 101 denotes a P-type siliconsubstrate. A symbol 102 denotes an N⁺-type buried layer. A symbol 103denotes an N-type collector layer. A symbol 104 denotes an undoped SiGelayer. A symbol 105 denotes an insulation separation oxide film. Asymbol 106 denotes a diffusion layer to pull out a collector. A symbol107 denotes an oxide film. A symbol 108 denotes a P-type poly-crystalsilicon layer to pull out an outer base. A symbol 109 denotes a siliconnitride film. A symbol 110A denotes a first SiGe base layer. A symbol110B denotes a second SiGe base layer. A symbol 111 denotes a siliconnitride film. A symbol 112 denotes a poly-crystal silicon film to pullout an emitter. And, a symbol 113 denotes an emitter layer.

[0079] In FIG. 4, the N⁺-type buried layer 102 having a highconcentration and the N-type collector layer 103 having a lowconcentration are formed on the P-type silicon substrate 101. Theundoped SiGe layer 104 in which impurity is not doped, the first SiGebase layer 110A having a first Ge concentration distribution, and thesecond SiGe base layer 110B having a second Ge concentrationdistribution are formed on the N-type collector layer 103 having the lowconcentration. And, the emitter layer 113 constituted by an N-typediffusion layer is formed on the second SiGe base layer 110B.

[0080]FIG. 5 is a graph showing the profile (slant Ge profile) of a Gepercent content and an impurity concentration with respect to a depth ofthe SiGe base bipolar transistor (semiconductor device) according to thefirst embodiment. In this embodiment, the N-type collector layer 103having the low concentration in which the N-type impurity is doped atabout 10¹⁶ cm⁻³ is formed on the N⁺-type buried layer 102 having thehigh concentration in which the N-type impurity is doped at about 10²⁰cm⁻³. Then, the undoped SiGe layer 104 having a Ge concentration ofabout 10% and a thickness of about 30 nm, the first SiGe base layer 110Ahaving the first Ge concentration distribution, and the second SiGe baselayer 110B having the second Ge concentration distribution are formed onthe N-type collector layer 103 having the low concentration. P-typeimpurity is doped at about 1×10¹⁹ cm⁻³ on the first SiGe base layer 110Aand the second SiGe base layer 110B. Moreover, the poly-crystal siliconfilm 112 to pull out an emitter in which the N-type impurity is doped atabout 2×10²⁰ cm⁻³ is formed on the second SiGe base layer 110B. Theemitter layer 113 is formed by using the impurity thermal diffusion fromthe poly-crystal silicon film 112 to pull out the emitter in which theN-type impurity is doped.

[0081] The undoped SiGe layer 104 in this embodiment is formed in orderto protect a parasitic energy barrier from being induced in abase-collector junction. By the way, as described in the conventionaltechnique disclosed in Japanese Laid Open Patent Application(JP-A-Heisei, 7-147287), the Ge distribution in the collector layer maybe designed so as to be sharply reduced on the side of a P-type SiGebase layer 210 and slowly reduced on the side of an N⁺-type buried layer202.

[0082] An embodiment of a semiconductor manufacturing method in thepresent invention will be described below. As shown in FIG. 2, this isdesigned such that a thickness of the second SiGe base layer 110B is setat about 20 nm, and a Ge concentration is increased from about 0% toabout 2% in the emitter region side of the second SiGe base layer 110B.And, this is designed such that a thickness of the first SiGe base layer110A is set at about 10 nm, and a Ge concentration is increased fromabout 2% to about 10% in the first SiGe base layer 110A.

[0083] Thus, in the second SiGe base layer 110B in which an emitter-basejunction and a depletion layer are formed, a Ge inclination (germaniuminclination) can be set at about 0.1%/nm. Hence, a variation amount of aband gap in the depletion layer becomes at an untroubled level, at atime of an increase in a base-emitter voltage.

[0084] On the other hand, the total Ge concentration inclinationresulting from the first SiGe base layer 110A and the second SiGe baselayer 110B is about 10%. Thus, the total of electric fields caused byslant energy band structure can be set to be equal to that of the casewhen the conventional Ge concentration has a constant inclination. As aresult, this provides the effect that the influence on a cut-offfrequency fT can be kept to a minimum.

[0085]FIG. 6 is a graph describing a change in a current gain hFE withrespect to a collector current density Jc.

[0086] In the conventional technique, as the collector current densityJc is higher, the current gain hFE is outstandingly dropped. On thecontrary, in this embodiment, the problem of the drop in the currentgain hFE is improved as shown in FIG. 6. Actually in this embodiment,the range of the collector current density Jc, in which the current gainhFE is within about 80% with respect to the maximum, can be enlarged byabout 20% as compared with that of the conventional technique. Also, thevariation in the collector current density Jc can be improved by about30%.

[0087] (Second Embodiment)

[0088]FIG. 7 is a graph showing the profile (slant Ge profile) of a Gepercent content and an impurity concentration with respect to a depth ofa SiGe base bipolar transistor (semiconductor device) according to asecond embodiment. In FIG. 7, a symbol 302 denotes an N⁺-type buriedlayer. A symbol 303 denotes an N-type collector layer. A symbol 304denotes an undoped SiGe layer. A symbol 310A denotes a third SiGe baselayer. A symbol 310B denotes a fourth SiGe base layer. A symbol 310Cdenotes a Si base layer. A symbol 312 denotes a poly-crystal siliconfilm to pull out an emitter. And, a symbol 313 denotes an emitter layer.

[0089] In the SiGe base bipolar transistor (semiconductor device)according to this embodiment, the N-type collector layer 303 having thelow concentration in which the N-type impurity is doped at about 10¹⁶cm⁻³ is formed on the N⁺-type buried layer 302 having the highconcentration in which the N-type impurity is doped at about 10²⁰ cm⁻³.Then, the undoped SiGe layer 304 having a Ge concentration of about 10%and a thickness of about 30 nm, the third SiGe base layer 310A having athird Ge concentration distribution, the fourth SiGe base layer 310Bhaving a fourth Ge concentration distribution, and the Si base layer310C are formed on the N-type collector layer 303 having the lowconcentration. The P-type impurity is doped at about 1×10¹⁹ cm⁻³ on thethird SiGe base layer 310A, the fourth SiGe base layer 310B and the Sibase layer 310C. Moreover, the poly-crystal silicon film 312 to pull outan emitter in which the N-type impurity is doped at about 2×10²⁰ cm⁻³ isformed on the Si base layer 310C. The emitter layer 313 is formed byusing the impurity thermal diffusion from the poly-crystal silicon film312 to pull out the emitter in which the N-type impurity is doped.

[0090] As shown in FIG. 7, in this embodiment, the thickness of the Sibase layer 310C is set at about 20 nm. Then, the thickness of the fourthSiGe base layer 310B is set at about 5 nm, and the Ge concentration isdesigned so as to be increased from about 0% to about 2% on the emitterregion side in the fourth SiGe base layer 310B. Then, the thickness ofthe third SiGe base layer 310A is set at about 5 nm, and the Geconcentration is designed so as to be increased from about 2% to about10% in the third SiGe base layer 310A.

[0091] In this embodiment, the emitter-base junction and its depletionlayer are formed in the Si base layer. Thus, this provides the effectthat the variation in the collector current and the linearity of thecurrent gain hFE can be further improved by respectively about 10% ascompared with the first embodiment.

[0092] By the way, it is obvious that the present invention is notlimited to the above-mentioned embodiments and that the above-mentionedembodiments can be suitably modified within the range of the technicalprinciple in the present invention. Also, the numbers, the positions andthe shapes of above-mentioned members and the like are not limited tothose of the above-mentioned embodiments. They may be the preferablenumbers, positions and shapes and the like, respectively. Also, in therespective drawings, the same symbols are given to the same members.

[0093] The present invention, since having the above-mentionedconfiguration, can provide the effect that the drop in the current gainis kept to the minimum, when the substrate density is amplified and thatthe variation in the collector current is improved.

What is claimed is:
 1. A semiconductor with a SiGe base bipolartransistor manufacturing method, comprising: (a) providing an emitterlayer; (b) providing a collector layer; and (c) providing a SiGe baselayer formed of silicon containing germanium, and wherein a Geconcentration of said SiGe base layer is increased from 0% to 10% from aside of said emitter layer towards a side of said collector layer. 2.The semiconductor with a SiGe base bipolar transistor manufacturingmethod according to claim 1, further comprising: (d) providing a P-typesilicon substrate; and (e) forming an N⁺-type buried layer having a highconcentration in said P-type silicon substrate, and wherein saidcollector layer is formed of an N-type having a low concentration and isformed on said N⁺-type buried layer, and wherein said semiconductor withsaid SiGe base bipolar transistor manufacturing method furtherincluding: (f) forming an undoped SiGe layer in which an impurity is notdoped on said N-type collector layer; (g) forming a first SiGe baselayer as a part of said SiGe base layer having a first Ge concentrationdistribution on said undoped SiGe layer; and (h) forming a second SiGebase layer as another part of said SiGe base layer having a second Geconcentration distribution on said first SiGe base layer, and whereinsaid emitter layer is formed of an N-type diffusion layer formed in saidsecond SiGe base layer.
 3. The semiconductor with a SiGe base bipolartransistor manufacturing method according to claim 2, wherein an N-typeimpurity is doped at about 10¹⁶ cm⁻³ as said low concentration of saidN-type collector layer, and said N-type impurity is doped at about 10²⁰cm⁻³ as said high concentration of said N⁺-type buried layer.
 4. Thesemiconductor with a SiGe base bipolar transistor manufacturing methodaccording to claim 3, wherein said undoped SiGe layer has a Geconcentration of about 10% and a thickness of about 30 nm.
 5. Thesemiconductor with a SiGe base bipolar transistor manufacturing methodaccording to claim 4, wherein a P-type impurity is doped at about 1×10¹⁹cm⁻³ in said first SiGe base layer and said second SiGe base layer. 6.The semiconductor with a SiGe base bipolar transistor manufacturingmethod according to claim 5, further comprising: (i) forming apoly-crystal silicon film to pull out an emitter in which an N-typeimpurity is doped at about 2×10²⁰ cm⁻³ on said second SiGe base layer.7. The semiconductor with a SiGe base bipolar transistor manufacturingmethod according to claim 6, wherein said emitter layer is formed as aresult that an impurity thermal diffusion is performed on saidpoly-crystal silicon film.
 8. The semiconductor with a SiGe base bipolartransistor manufacturing method according to claim 1, wherein said SiGebase layer includes a first SiGe base layer and a second SiGe baselayer, and wherein a thickness of said second SiGe base layer is about20 nm, and a Ge concentration in said second SiGe base layer isincreased from about 0% to about 2% from said side of said emitter layertowards said side of said collector layer, and wherein a thickness ofsaid first SiGe base layer is about 10 nm, and a Ge concentration insaid first SiGe base layer is increased from about 2% to about 10% fromsaid side of said emitter layer towards said side of said collectorlayer.
 9. The semiconductor with a SiGe base bipolar transistormanufacturing method according to claim 1, further comprising: (j)providing a P-type silicon substrate; and (k) forming an N⁺-type buriedlayer having a high concentration in which an N-type impurity is dopedat about 10²⁰ cm⁻³ in said P-type silicon substrate, and wherein saidcollector layer is formed of an N-type having a low concentration inwhich said N-type impurity is doped at about 10¹⁶ cm⁻³ and is formed onsaid N⁺-type buried layer, and wherein said semiconductor with said SiGebase bipolar transistor manufacturing method further including: (l)forming an undoped SiGe layer in which an impurity is not doped on saidN-type collector layer, said undoped SiGe layer having a Geconcentration of about 10% and a thickness of about 30 nm; (m) forming athird SiGe base layer as a part of said SiGe base layer having a thirdGe concentration distribution on said undoped SiGe layer; (n) forming afourth SiGe base layer as another part of said SiGe base layer having afourth Ge concentration distribution on said third SiGe base layer; and(o) forming a Si base layer as other part of said SiGe base layer. 10.The semiconductor with a SiGe base bipolar transistor manufacturingmethod according to claim 9, wherein a P-type impurity is doped at about1×10¹⁹ cm⁻³ in said third SiGe base layer, said fourth SiGe base layerand said Si base layer.
 11. The semiconductor with a SiGe base bipolartransistor manufacturing method according to claim 10, furthercomprising: (p) forming a poly-crystal silicon film to pull out anemitter in which an N-type impurity is doped at about 2×10²⁰ cm⁻³ onsaid Si base layer.
 12. The semiconductor with a SiGe base bipolartransistor manufacturing method according to claim 11, wherein saidemitter layer is formed as a result that an impurity thermal diffusionis performed on said poly-crystal silicon film.
 13. The semiconductorwith a SiGe base bipolar transistor manufacturing method according toclaim 1, wherein said SiGe base layer includes a third SiGe base layerand a fourth SiGe base layer, and a Si base layer, and wherein athickness of said Si base layer is about 20 nm, and wherein a thicknessof said fourth SiGe base layer is about 5 nm, and a Ge concentration insaid fourth SiGe base layer is increased from about 0% to about 2% fromsaid side of said emitter layer towards said side of said collectorlayer, and wherein a thickness of said third SiGe base layer is about 5nm, and a Ge concentration in said third SiGe base layer is increasedfrom about 2% to about 10% from said side of said emitter layer towardssaid side of said collector layer.